RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design [Print Replica] Kindle Edition

While the title of this book says it's "for Simulation and Synthesis", the emphasis in the text is clearly on the latter. Mr. Sutherland (who tragically passed away suddenly in 2018) has long advocated for the synthesis features of SystemVerilog in his conference papers and training seminars.This is more than just an update to Mr. Sutherland's earlier book, "SystemVerilog for Design". The earlier book focused mainly on how SystemVerilog differed from the original Verilog language, and its target audience was experienced Verilog designers looking to understand and take advantage of the new SystemVerilog features. This new book dispenses with most of that (but not all), and details SystemVerilog as though the reader is not already familiar with Verilog. However, I can't assess how well this book serves a reader who is completely new to SystemVerilog or HDL-based design.As one who has used Verilog since 1994 and SystemVerilog since 2012, for both synthesis and simulation of FPGAs, I found this book to be extremely useful and readable, and I picked up a number of language features and "tricks" which I wasn't previously aware of. I especially liked how he summarizes the key principles of each chapter at the end, and the numerous "Best Practice Guides" distributed throughout the text with recommendations--and explanations--based on real-world use. It has a thorough index, which is also important for use as a reference.I also recommend, as a companion reference, Chris Spear's also excellent "SystemVerilog for Simulation".

This book is up to date and comprehensive. Love the best practices advice in each section. Not just the best SystemVerilog book, but one of the best hardware modeling books out there.

The content of book covers latest standard Systemverilog 2017 as it states, the author did a great job to make his book very organized and easy to understand. Excellent language structure! I had read many technical book and found somehow this book is by far reader friendly! Definitely recommend to everyone who wants to learn SystemVerilog!

After reading the book, one gains enough knowledge of the synthesizable subset of SystemVerilog. Consulting the standard will still be needed.What did surprise me is that generate statements were never mentioned.There were some minor typos and text repetitions. Nevertheless, it’s a really good book.

This is exactly the book I was looking for. It's comprehensive and the author uses a friendly, easy to read writing style. If you're using Verilog (System Verilog, really), then this is the book you want.

excellent book, very complete on rtlmodels with system verilog. Poor on simular5ion, though.

Lacks any mention of arrays of module instances, a SV feature that greatly simplifies designs that have replicated sub-modules. For an otherwise thorough reference this seems a major omission.

Nice book

SytemVerilog is Verilog on steroids. Although most of new stuff in SV is about the testbench, there are enough additions to the synthesisable subset that it elevates the language to a new level. Especially for large designs the concepts of structures, interfaces, enumerators etc are really useful, making the code more understandable while removing a lot of error-prone repeated typing. Additional constructs help to avoid gotchas like inadvertent latch inference from a missed path in a combinatorial always block and similar.This book largely ignores the testbench aspect of SV and focuses on RTL level descriptions. It is really good at telling you what's new in SV and how to use those new features. The book says that you don't need to know Verilog to understand it, and since I do know Verilog, I can't really judge whether that is true or not, but I do believe that if you don't know how HDL-based HW design works, you'll have a really hard time to understand the book. In addition, the book occasionally refers to previous Verilog constructs, if for nothing else, to show how the new SV version helps you or how it differs from the old version. Furhermore, SV is a proper superset of Verilog, any Verilog code is also valid SV code (and you can even set what Verilog standard the old code is written) so I think this book is really not for someone who wants to start designing chips and needs to learn how, but someone who is comfortable with Verilog and now wants to move to the next level in design complexity.Some constructs, like "generate", are simply missing from the book and a few other handy aspects of Verilog (or SV) got only a mention, hence the 4 starts instead of 5, but that's the only flaw I could find.Nevertheless, if you are a Verilog engineer writing RTL code and want to make your life easier by using SV, then this book is definitely for you. You'll need other books (which are abundant) on the simulation and testbench aspects of the language (those constructs are not even mentioned in this book, and deliberately so) but for the synthesisable subset, this is the book you want. I can wholeheartedly recommend it.

Stuart Sutherland is the author covering both Verilog and SystemVerilog topics with great authority, confidence and expertise.If there is one book to have on using SysteVerilog for RTL synthesis - this would be my recommendation.There is virtually no aspect of using SystemVerilog for FPGA (and / or asic) implementation that is left out of the scope of this book.Very detailed, clear and thorough presentation of all relevant topics in the field.However - keep in mind that SystemVerilog language constructs and features for verification space are NOT covered in this book. That may not be all that clear from the book cover and title. It is clarified in the book preface and introduction though.Highly recommended reference book.